A traditional ASIC (Application Specific Integrated Circuit) project for an integrated electronic circuit, for example, of the digital type, may provide for a definition of the specifications of the circuit and a description thereof by way of a programming language (software). In a subsequent synthesis operation, the description of the circuit is used for transforming the project into a list of components, i.e. into logic cells, and connections between the cells which provide macroblocks to be implemented via circuitry (hardware). The list of components and connections or netlist is transformed into a physical drawing or layout of the digital circuit using commercial CAD software.
In particular, the layout of the circuit comprises single or multiple cells belonging to a standard cell library suitable to operate in a combinatory manner (for example, Inverter, NAND, NOR) and in a sequential manner (for example, Flip Flop, Latch). Depending on the complexity of the ASIC, the layout of the digital circuit may comprise multiple base layers, multiple contacts and multiple metal layers. The procedure for providing models of layers is commonly referred to as tape-out.
Modifications for eliminating, or adding, logic elements and interconnections from the initial layout of the circuit are used after tape-out to perform subsequent project variations. When this occurs, an engineering change order (ECO) is generated to document the desired variations.
In typical EGO methods, supplementary logic spare cells, or configurable filler cells, of different type are included in the initial computerized layout as reserves in case new elements are required or implementation of new functionalities in the circuit structure is required. Traditionally, the CAD software operates to place and route the cells on a grid having a pitch defined by the technological process. Generally, the space between two adjacent cells in the grid is null or multiple with respect to the pitch.
In each technology for semiconductor integrated circuits, the pitch of the placement grid is equivalent to the width of the smallest filler cell available for that technology. For example, a minimum pitch value Pm is calculated by the relation:Pm=2.5×l; where L is the channel length characteristic of the technology employed.
In conventional EGO applications, the digital filler cells included in the layout have a width equivalent to a multiple of the minimum pitch value Pm of the standard minimum cell of the technology. The typical ECO cells may reveal disadvantages related to the placing and interconnection thereof according to the space restrictions defined in the layout. Furthermore, the typical ECO approaches may use excessive area on the silicon chip mostly to the detriment of the applications.